library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;


entity reg is
generic (N : integer :=32);
port( 	clock	: in   std_logic;
		reset	: in   std_logic;
		enable	: in   std_logic;
		data_in 	: in   std_logic_vector (N-1 downto 0);
		data_out	: out std_logic_vector (N-1 downto 0)
);
end reg;

architecture Behavioral of reg is
begin
	
	REG: entity work.ffdcN(structural) generic map(N)
	port map (clock,reset,enable,data_in,data_out);

end Behavioral;
